Flash memory devices are nonvolatile memory devices that retain stored data even when the memory device is not connected to an external power supply. Flash memory devices include both NOR and NAND type flash memories. A conventional NOR-type flash memory device has a memory cell array region that includes a plurality of cell transistors, a plurality of bitlines, and a plurality of source lines. Each cell transistor may be disposed at the intersection of one of the bitlines and one of the source lines. A conventional NAND-type flash memory device has a plurality of cell strings in a cell array region. A unit cell string includes a string selection transistor, a plurality of cell transistors, and a ground selection transistor that are connected in series. The drain of the string selection transistor is connected to a bitline, while the source of the ground selection transistor is connected to a common source region. The cell transistors in the unit cell string are configured to share the single bitline and source region. As such, a conventional NAND-type flash memory device may provide for a higher degree of integration than a conventional NOR-type flash memory device.
FIGS. 1 and 2 are cross-sectional diagrams illustrating a conventional method of fabricating a NAND-type flash memory device. Referring to FIG. 1, field isolation films (not shown) are formed to define active regions in a semiconductor substrate 1. A string-selection gate line 3s, a plurality of cell gate lines 3a, and a ground-selection gate line 3g are formed on the semiconductor substrate 1 to cross over the active regions. The gate lines, 3s, 3a, and 3g, are arranged in parallel with each other. The cell gate lines 3a are disposed between the string-selection gate line 3s and the ground-selection gate line 3g. Each of the cell gate lines 3a includes a tunnel oxide film, a floating gate, an oxide-nitride-oxide (ONO) film, and a control gate that are sequentially stacked on the substrate 1.
Impurity ions are selectively implanted to form a common drain region 5d, cell source/drain regions 5a, and a common source region 5s. The common drain region 5d is formed at one side of the string-selection gate line 3s, the cell source/drain regions 5a are formed at both sides of the cell gate lines 3a, and the common source region 5s is formed at one side of the ground-selection gate line 3g. The gate lines 3s, 3a, and 3g, and the cell source/drain regions 5a are arranged between the common drain region 5d and the common source region 5s. 
A first interlayer oxide film 7 is formed on the semiconductor substrate 1. The first interlayer oxide film 7 is patterned to form an opening 9 that exposes the common source region 5s. The opening 9 may be formed in the shape of groove crossing the active region. A conductive film (not shown) may be formed on the semiconductor substrate 1 in order to fill the opening 9. This conductive film is planarized until the first interlevel oxide film 7 is exposed to form a source line 11 in the opening 9.
As shown in FIG. 2, a second interlayer oxide film 13 is deposited over the semiconductor substrate 1. The second and first interlayer films 13 and 7 are patterned to form a bitline contact hole 15 that exposes the common drain region 5d. A contact plug 17 is formed in the bitline contact hole 15, and a bitline 19 is formed on the second interlayer oxide film 13. The bitline 19 is in electrical contact with the contact plug 17.